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PRELIMINARY
W48S101-04
Spread Spectrum Motherboard Frequency Generator
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * I2CTM interface * Four copies of CPU output * Eight copies of PCI clock (synchronous w/CPU output) * Two copies of 14.318-MHz IOAPIC output * One copy of 48-MHz USB output * Selectable 24-/48-MHz clock-through-resistor strapping * Three buffered copies of 14.318-MHz reference input * Input is a 14.318-MHz XTAL or reference signal * Selectable 100-MHz or 66-MHz CPU outputs * Power management control input pins * Test mode and output three-state through I2C interface
Key Specifications
Supply Voltages:....................................... VDDQ3 = 3.3V5% VDDQ2 = 2.5V5% CPU Cycle to Cycle Jitter: ........................................... 200 ps CPU0:3 Output Skew: ................................................ 175 ps PCI_F, PCI1:7 Output Skew: .......................................500 ps CPU to PCI Output Skew: ............ 1.5 to 4.0 ns (CPU Leads) Logic inputs and REF0/SEL48# have 250K pull-up resistors except SEL100/66#. Table 1. Pin Selectable Frequency SEL 100/66# 0 1 CPU (MHz) 66.8 100
[1]
PCI (MHz) 33.4 33.3
SPREAD#=0 0.5% Center 0.5% Center
Block Diagram
VDDREF REF0/SEL48# X1 X2 XTAL OSC PLL Ref Freq VDDCORE0/1 GNDCORE0/1 REF1 REF2 GNDREF VDDAPIC APIC0 APIC1 GNDAPIC VDDCPU0 CPU0 Stop Clock Control 100/66#_SEL PLL 1 /2//3 SPREAD# CPU1 GNDCPU0 VDDCPU1 CPU2 CPU3 GNDCPU1 VDDPCI0 PCI_F Stop Clock Control PCI_STOP# PCI1 PCI2 PCI3 GNDPCI0 VDDPCI1 PCI4 I 2C Logic Power Down Control PLL2 PCI5 PCI6 PCI7 PWR_DWN# GNDPCI1 VDD48MHz 48MHz 24/48MHz GND48MHz I2C is a trademark of Philips Corporation.
Pin Configuration
REF0/SEL48# REF1 GNDREF X1 X2 GNDPCI0 PCICLK_F PCI1 VDDPCI0 PCI2 PCI3 GNDPCI1 PCI4 PCI5 VDDPCI1 PCI6 PCI7 GNDPCI2 VDDCORE0 GNDCORE0 VDD48MHz 48MHz 24/48MHz GND48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CPU_STOP#
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDREF REF2 VDDAPIC APIC0 APIC1 GNDAPIC NC VDDCPU0 CPU0 CPU1 GNDCPU0 VDDCPU1 CPUCLK2 CPUCLK3 GNDCPU1 VDDCORE1 GNDCORE1 PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SDATA SCLK SEL100/66#
Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH.
SDATA SCLK
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 October 27, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:3 Pin No. 40, 39, 36, 35 8, 10, 11, 13, 14, 16, 17 7 Pin Type O Pin Description
W48S101-04
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. CPU_STOP# Input: When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 start beginning with a full clock cycle (2-3 CPU clock latency). PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle. SPREAD# Input: When brought LOW this pin activates Spread Spectrum clocking. I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 48-MHz Output: Fixed clock outputs at 48 MHz. Output voltage swing is controlled by voltage applied to VDDQ3. 24-MHz or 48-MHz Output: 24-MHz output when pin 1 is strapped through 10-k resistor to VDDQ3. 48-MHz output when pin 1 is strapped through 10-k resistor to GND. I/O Dual Function REF0 and SEL48# pin: During power on, SEL48# input will be latched, which will set pin 23 to output 24 MHz or 48 MHz. It then reverts to REF0 fixed output. Fixed 14.318-MHz Outputs 1 through 2: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency Selection Input: Selects power-up default CPU clock frequency as shown in Table 1 on page 1. Clock pin for I2C circuitry. Data pin for I2C circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Down Control: When this input is LOW, device goes into a low-power standby condition. All outputs are actively held LOW while in power-down. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2-3 CPU clock cycle latency). When brought HIGH, CPU, SDRAM and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). Power Connection: Connect to 3.3V supply. Power Connection: Power supply for APIC0:1 and CPU0:3 output buffers. Connect to 2.5V. Ground Connections: Connect all ground pins to the common system ground plane.
PCI1:7
O
PCI_F
O
CPU_STOP#
30
I
PCI_STOP#
31
I
SPREAD# APIC0:1 48MHz 24/48MHz
28 45, 44 22 23
I O O O
REF0/SEL48#
1
I/O
REF1:2 SEL100/66# SCLK SDATA X1
2, 47 25 26 27 4
O I I I/O I
X2 PWR_DWN#
5 29
I I
VDDQ3 VDDQ2 GND
9, 15, 19, 21, 33, 48 46, 41, 37 3, 6, 12, 18, 20, 24, 32, 34, 38, 43
P P G
2
PRELIMINARY
Overview
The W48S101-04, a motherboard clock synthesizer, can provide either a 2.5V or 3.3V CPU clock swing, making it suitable for a variety of CPU options. A fixed 48-MHz clock is provided for other system functions. The W48S101-04 supports spread spectrum clocking for reduced EMI.
W48S101-04
strapping resistor on the l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic "0" or "1" condition of the l/O pin is then latched. Next the output buffer is enabled, which converts the l/O pin into an operating clock output. The 2-ms timer is started when V DD reaches 2.0V. The input bit can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistor has no significant effect on clock output signal integrity. The drive impedance of clock output is 40 (nominal) which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock output is enabled following the 2-ms input period, a 14.318-MHz output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
Functional Description
I/O Pin Operation Pin 1 is a dual-purpose l/O pin. Upon power-up this pin acts as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of the pin is latched and the pin becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon W48S101-04 power-up, the first 2 ms of operation is used for input logic selection. During this period, the Reference clock output buffer is three-stated, allowing the output
VDD Output Strapping Resistor 10 k (Load Option 1) W48S101-04 Power-on Reset Timer Output Buffer Output Three-state
Q
Series Termination Resistor Clock Load
Hold Output Low
D
10 k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options VDD 10 k W48S101-04 Power-on Reset Timer Output Buffer Output Three-state
Q
Output Strapping Resistor Series Termination Resistor R Clock Load
Hold Output Low
D
Resistor Value R
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
3
PRELIMINARY
Spread Spectrum Clock Generation
The benefits of using Spread Spectrum Clock Generation are depicted in Figure 3. An EMI emission profile of a clock harmonic is shown.
W48S101-04
Contrast the typical clock EMI with the Cypress Spread Spectrum Clock Generation. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With the Cypress clock, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth.
5dB/div
SS FT G
Typ ical C lo ck
Amplitude (dB)
-SS %
Freq uen cy Sp an (M Hz)
+S S%
Figure 3. Typical Clock and SSCG Comparison
MAX (+0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN (-0.5%)
Figure 4. Typical Modulation Profile
4
100%
PRELIMINARY
Serial Data Interface
The W48S101-04 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W48S101-04 initializes with default register settings. Therefore, the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic Table 2. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Common Application
W48S101-04
outputs of the chipset. Clock device register changes are normally made upon system initialization, if required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the W48S101-04 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3.
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused PCI slots. Provides CPU/PCI frequency selections beyond the 100- and 66.6-MHz selections that are provided by the SEL100/66# pin. Frequency is changed in a smooth and controlled fashion. Puts all clock outputs into a high-impedance state. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing.
CPU Clock Frequency Selection
Output Three-state Test Mode (Reserved)
All clock outputs toggle in relation to X1 input, inter- Production PCB testing. nal PLL is bypassed. Refer to Table 4. Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0.
Table 3. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W48S101-04 to accept the bits in Data Bytes 3-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W48S101-04 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W48S101-04, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W48S101-04, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Refer to Cypress SDRAM drivers.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Don't Care
Refer to Table 4
The data bits in these bytes set internal W48S101-04 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
5
PRELIMINARY
Writing Data Bytes Each bit in the data bytes controls a particular device function except for the "reserved" bits, which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 4 gives the bit formats for registers located in Data Bytes 3-6. Table 4. Data Bytes 3-6 Serial Configuration Map Affected Pin Bit(s) Pin No. Pin Name -----Control Function (Reserved) SEL_2 SEL_1 SEL_0 BYT0_FS# 0 -Refer to Table 5 Refer to Table 5 Refer to Table 5 Frequency Controlled by external SEL100/ 66# pin -Data Byte 3 7 -6 5 4 3 ----Bit Control 1 --
W48S101-04
Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 3, bits 1 and 0.
Default 0 0 0 0 0
Frequency Controlled by BYT0 SEL (2:0) --
2 1-0
---
---
(Reserved) Bit 1 0 0 1 1 Bit 0 0 1 0 1
0 00
Function (See Table 6 for function details) Normal Operation Test Mode Spread Spectrum on (See Table 5 for frequency and spread selections. 0.5% modulation) All Outputs Three-stated -Low --Low Low Low Low Low Low Low Low Low Low Low Low --Low Low -Low Low Low -Active --Active Active Active Active Active Active Active Active Active Active Active Active --Active Active -Active Active Active
Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 --44 45 -47 2 1 --IOAPIC1 IOAPIC0 -REF2 REF1 REF0 (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable 0 0 1 1 0 1 1 1 -23 --35 36 39 40 7 17 16 14 13 11 10 8 -24/48MHz --CPU3 CPU2 CPU1 CPU0 PCICLK_F PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 (Reserved) Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
6
PRELIMINARY
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 3, Bit 3 = 1 Bit 6 SEL_2 0 0 0 0 1 1 1 1 Bit 5 SEL_1 0 0 1 1 0 0 1 1 Bit 4 SEL_0 0 1 0 1 0 1 0 1 CPU, SDRAM Clocks (MHz) 68.5 75 83.3 66.8 103 112 133.3 100 PCI Clocks (MHz) 34.25 37.5 41.6 33.4 34.33 37.33 44.43 33.3 Output Frequency
W48S101-04
Spread Percentage with Spread Spectrum turned on 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center
Table 6. Select Function for Data Byte 3, Bits 0:1 Input Conditions Data Byte 3 Function Normal Operation Test Mode Spread Spectrum On Three-state Bit 1 0 0 1 1 Bit 0 0 1 0 1 CPU0:3 Note 2 X1/2 Note 2, 55%0.5 Hi-Z PCI_F, PCI1:7 Note 2 CPU/2, 3, or 4 Note 2, 55%0.5 Hi-Z Output Conditions REF0:2, IOAPIC0:1 14.318 MHz X1 14.318 MHz Hi-Z 48MHZ 48 MHz X1/2 48 MHz Hi-Z 24MHZ 24 MHz X1/4 24 MHz Hi-Z
Note: 2. CPU and PCI frequency selections are listed in Table 1 and Table 5.
7
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TA TB ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
W48S101-04
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDDQ3 IDDQ3 Logic Inputs VIL VIH IIL IIH IIL IIH VOL VOH VOH IOL Input Low Voltage Input High Voltage Input Low Current[4] Input High Current[4] Input Low Current (SEL100/66#) Input High Current (SEL100/66#) Output Low Voltage Output High Voltage Output High Voltage Output Low Current (CPU, APIC) CPU0:3 PCI_F, PCI1:7 APIC0:1 REF0:2 48MHz 0:1 IOH Output High Current CPU0:3 PCI_F, PCI1:7 APIC0:1 REF0:2 48MHz 0:1 IOL = 1 mA IOH = -1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V 3.1 2.2 27 20.5 40 25 25 25 31 40 27 27 57 53 85 37 37 55 55 87 44 44 97 139 140 76 76 97 189 155 94 94 GND - 0.3 2.0 0.8 VDD + 0.3 -25 10 -5 5 50 V V A A A A mV V V mA mA mA mA mA mA mA mA mA mA 3.3V Supply Current 2.5V Supply Current CPUCLK =100 MHz Outputs Loaded[3] 120 60 mA mA Description Test Condition Min. Typ. Max. Unit
Clock Outputs
Notes: 3. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section. 4. W48S101-04 logic inputs have internal pull-up devices, except SEL100/66#.
8
PRELIMINARY
W48S101-04
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[5] Load Capacitance, as seen by External Crystal[6] X1 Input Capacitance[7] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 1.5 14 28 5 6 7 V pF pF pF pF nH Description Test Condition Min. Typ. Max. Unit
Pin Capacitance/Inductance
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%,VDDQ2 = 2.5V 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 15 5.2 5.0 1 1 45 4 4 55 200 15.5 CPU = 100 MHz Typ. Max. Unit 10.5 ns ns ns 4 4 55 250 V/ns V/ns % ps 10 3.0 2.8 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
Notes: 5. X1 input threshold voltage (typical) is VDD/2. 6. The W48S101-04 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
9
PRELIMINARY
PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF
W48S101-04
CPU = 66.8/100 MHz Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1.5 Min. 30 12 12 1 1 45 4 4 55 250 500 4 3 Typ. Max. Unit ns ns ns V/ns V/ns % ps ps ns ms
Zo
APIC0:1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.8/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 1 45 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
REF0:2 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.8/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
10
PRELIMINARY
48MHz0:1 Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz)
W48S101-04
CPU = 66.8/100 MHz Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
Ordering Information
Ordering Code W48S101 Document #: 38-00853 Freq. Mask Code -04 Package Name H Package Type 48-pin SSOP (300 mils)
11
PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W48S101-04
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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